1. Field of the Invention
The present invention generally relates to plasma display panels and, more specifically, to the control of a plasma display panel power stage.
2. Description of the Related Art
A plasma display panel is formed of an array of cells arranged at the intersection of lines and columns. Each cell of the display panel comprises a cavity filled with a gas and at least two control electrodes. To create a light spot on the display panel by using a given cell, a potential difference is applied between the control electrodes thereof, the gas contained in the cell being then ionized, generally by means of a third electrode. This ionization comes along with an ultraviolet ray emission, the light spot creation being obtained by excitation of a red, green, or blue light-emitting material by these rays.
FIG. 1 very schematically shows in the form of blocks a conventional example of a plasma display panel formed of a network of cells represented in FIG. 1 by their equivalent capacitances 2. Each cell comprises two electrodes respectively connected to a line 4 and to a column 6. A line control circuit 8 (SCAN) comprises, for each line 4, an activation/deactivation circuit having an output connected to the considered line. A column control circuit 12 comprises an element 16 (DATA) (generally of shift register type) for parallelizing address data received in series (signal COL) and, for each column 6, a control circuit or stage 14 having an output O connected to the considered column 6 and receiving, on input data E, reference signals generated from the luminance data. Elements 14 and 16 are generally integrated in a same circuit 12. A general circuit 10 (CTRL) for controlling the display panel synchronizes the operation of circuits 8 and 12.
The display panel cells are activated in a line scanning by means of circuit 8. The non-activated lines are submitted to a quiescent voltage (generally greater than 100 volts), while the activated line is brought to an activation voltage (generally, 0 volt). The quiescent voltage of a column corresponds to ground. To activate cells based on the data provided by circuit 16 on the active line, the corresponding columns are brought to an activation voltage Vpp generally on the order of 70 volts for a given period.
The voltage difference between an activated line and a column (about 70 volts) provides lighting of the selected cell. The third electrode (not shown in FIG. 1), called support electrode, provides for adjusting the luminance of the selected cells (memory effect).
FIG. 2 illustrates, in a very simplified partial representation of three control stages 14i−1, 14i, and 14i+1 of columns Ci−1, Ci, and Ci+1, a conventional example of precharge or predischarge of cells of a plasma display panel of the type shown in FIG. 1. The function is to limit the screen consumption to bring the respective column electrodes to the activation voltage. For example, an external capacitor with a capacitance greater than the total equivalent capacitance of the panel is used, to store power on discharge of a line which has just been addressed and prepare the charge of the next line. Each output terminal O of a circuit 14 is connected to the junction point of two switches P1 and N1 in series between two terminals of application of activation voltage VPP. Switches K connect terminals O to a terminal 24 which is at a voltage VPP/2 (for example, the first electrode of the capacitor, which has its second electrode at ground). The control of switches P1, N1, and K of each stage is organized to, between each line Lj, enable recovering charges of the columns to be discharged (cells to be turned off) for the benefit of columns to be charged (cells to be turned on). It is then spoken of charge sharing. Voltage VPP/2 of terminal 24 may also be obtained by an internal or external voltage source or by any other means. In FIG. 2, the cumulated equivalent capacitances of the cells of columns Ci−1, Ci, and Ci+1 have been represented by capacitances {2}i−1, {2}i, and {2}i+1 in dotted lines.
FIG. 3 shows the electric diagram of a circuit 14 for controlling a column (represented by its equivalent capacitance {2} in dotted lines). Switches P1 and N1 formed of MOS transistors, respectively with a P and N channel, in series between two terminals 20 and 22 of application of voltage VPP, are each in parallel with a diode D16 or D18 (for example, their respective parasitic diodes). The anode of diode D16 is connected to the drain of transistor P1 (output terminal O of the stage), the source of transistor P1 being connected to terminal 20. The anode of diode D18 is connected to ground 22, the source of transistor N1 being also connected to ground 22, and its drain being connected to terminal O. Bidirectional switch K is formed of two N-channel MOS transistors N2 and N3 in series and with a common source of terminal 24 at voltage VPP/2 and terminal O. Two diodes D26 and D28, for example corresponding to the parasitic diodes of transistors N2 and N3, have their respective anodes connected to midpoint 30 of switch K. The gates of transistors N2 and N3 are connected together to the drain of a P-channel MOS transistor P2, mirror-assembled on a P-channel MOS transistor P3. Transistor P3 is in series with a control transistor N4 and a current source 34 between terminal 20 and ground 22.
The control of circuit 14 is performed by means of three signals VH, VL, and VM. A level-shifting circuit 36 (LS), controlled by signal VH referenced to ground, is interposed between terminal 20 and the gate of transistor P1. Signal VL is directly applied to the gate of transistor N1 while signal VM is applied to that of transistor N4. The function of signals VL, VH, and VM is to control circuit 14 to organize the precharge and predischarge of the addressed cells between the actual display periods.
FIG. 4 very schematically shows in the form of blocks an amplifier 14 and partially shows column control circuit 16, to illustrate the different signals received by these circuits. Circuit 16 receives, from circuit 10, a signal CSE (Charge Sharing Enable) for controlling the precharge or predischarge and a synchronization signal Str. Signal CSE is active at state 1 while signal Str indicates, by ground pulses, the times of switching of the column data of the shift register of circuit 16 to circuits 14 for generation of signals Out.
FIGS. 5A, 5B, 5C, 5D, 5E, and 5F illustrate in timing diagrams the operation of amplifier 14 of FIGS. 3 and 4 for the lighting (signal DATA at 1) of a cell at the intersection of a line Lj and of the considered column Ci. In FIG. 5, preceding and next lines Lj−1 and Lj+1 are assumed not to have to be lit for the current column (signal DATA at 0).
Signals VL (FIG. 5C), VM (FIG. 5D), and VH (FIG. 5E) are generated by circuit 16 based on signals Str (FIG. 5A) and CSE (FIG. 5B) by taking into account the data to be displayed of the preceding columns. An example of a circuit for generating signals VL, VM, and VH is described in U.S. Pat. No. 7,122,968.
The function of signals VL, VM, and VH is to control amplifier 14 to obtain a precharge to level VPP/2 of the concerned column (voltage Vout, FIG. 5F) before completing this charge through transistor P1. Conversely, at the end of the column addressing, these signals are used to organize the cell discharge towards terminal 24 before ending this discharge through transistor N1.
Assuming that the datum of the preceding line Li−1 is 0, signals VM and VH are low until time t1 of the pulse of signal Str, so that transistors P1 and N4 are blocked while transistor N1 is on. At a time t0, preceding time t1 towards the end of the addressing of line Li−1, signal CSE is switched to state 1 to activate the charge transfer system. At time t1 when signal Str switches to the low state to transfer the data from the shift register to circuits 14, signal VL switches to the low state to block transistor N1 while signal VM switches to the high state to turn on transistor N4. Since terminal O is in the low state, this results in a turning-on of transistor N2 and a precharge (FIG. 5F) of node O approximately up to level VPP/2 via transistor N2 and diode D28, which is then forward biased. With a capacitor providing level VPP/2, the increase in voltage Vout actually lasts until the charges are balanced between this capacitor and the equivalent capacitances of the addressed display panel cells. At a time t2, signal CSE returns to the low state, which causes a low switching of the transistor of signal VM and a high switching of signal VH. This results in a turning-off of transistor N4, which in turn results in a turning-off of transistor N2 and of switch K, and a turning-on of transistor P1 to complete the charge of the cells of the addressed column up to level VPP. A little before the end of the addressing of current line Li (time t0′), signal CSE switches back to the high state, indicating an activation of the precharge or predischarge circuit. At a following time t1′, the pulse on signal Str causes the high switching of signal VM as at time t1 and due to the data level 0 desired for the next line Li+1, signal VH switches to the low state while signal VL remains therein. This results in a discharge of the cells charged to level VPP during the previous period to reach level VPP/2. As for the previous period, when signal CSE switches back to the low state (time t2′), this causes the carrying on of the discharge to 0 by the switching to the high state of signal VL and the turning-off of transistor N4 (switching to the low state of signal VM).
For the case where a next line in the scan order has to keep the same level, the predischarge (times t1′ to t2′) does not occur.
As compared with still prior solutions based on the use of a PMOS transistor to form switch K, the use of two DMOS transistors N2 and N3 space, a switch K having to be provided for each column.
However, a disadvantage of the circuit of FIG. 3 is a static consumption on turning-on of switch K.
Another disadvantage is a risk of simultaneous conduction of transistors N2 and N3 and of transistor P1 at time t2, causing a short-circuit between supply line 20 at level Vpp and terminal 24 at level VPP/2. The same problem occurs at time t2′ with the ground.
The risk of simultaneous conduction is partly linked to the stray capacitances of the gates of transistors N2 and N3 which, when added to the stray drain capacitance of transistor P1, generate a switching delay. The risk of simultaneous conduction also originates from the recovery time of diodes D26 or D28 according to the initial cell biasing.
An additional constraint in display panels of the type to which the present invention applies is that it is not desirable to multiply the number of input signals of the column control circuits, which are in practice made in an integrated circuit. This is among others justified by a need for a compatibility of the column control circuit with the rest of the circuits.